ETEE 3156 Lab VI









 







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The


William


States


Lee


College

of Engineering

 

The

University
of

North Carolina
at


Charlotte




 

ELET3132L

 


 



 



 



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Instructor:

Stephen J Kuyath

 

Phone:

704.687.4799

Email Address:

sjkuyath@uncc.edu



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ELET3132L Information:

Syllabus

 

Title Page

 

Writing Checklist

 

Oral Report Checklist

 



 

 

IEEE Writing Manual: Describes how to format Bibliographies and citations

 



 

 

Pinouts of 74 series Logic ICs

 



 

 

Lab Report Guidelines

 

Required Sections for Reports (Report Check Sheet)

 



 

Assignments:

Course Intro

 

 

Lab 1

Logic Gates and Families (using PSpice and MultiSIM

 

Lab 2

Logic Circuit Simplification using Boolean Algebra, Karnaugh Maps, and Multisim

 

Lab 3

Tutorial: Designing with FPGAs (using Xilinx WebPack, ver. 13.1)

 

Lab 4

Logic Circuit Simplification using Boolean Algebra, Karnaugh Maps, and Xilinx

 

Lab 5

Bi-Stable Latches and Flip Flops (using Xilinx WebPack, ver. 13.1)

 

Lab 6

MSI Data Selectors, Decoders, Multiplexers and Demultiplexers (using Xilinx WebPack, ver. 13.1)

 

Lab 7

Conversion between Analog and Digital Signals

 

 

Lab 8

State Machine Design: The Pump Problem (using Xilinx)

 

 

 

 

 

 

  More Labs to come

 



 

 

 

 



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Last Updated: August 19, 2010



 



 

Logic Circuit Simplification using Karnaugh Maps