Peer-Reviewed Journal Articles

J8. C. ZhangH. Tabkhi and G. Schirner, “Studying Inter-Warp Divergence Aware Execution on GPUs“, IEEE Computer Architecture Letters, in Press (accepted in 09/03/2015).

J7. H. TabkhiR. Bushey and G. Schirner, “Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications“, Springer Journal of Signal Processing and Systems, in Press (accepted in 09/21/2015).

J6. H. TabkhiR. Bushey and G. Schirner, “Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs“, Elsevier Journal of Microprocessors and Microsystems, vol.39, no.8, pp. 704-719, Nov. 2015.

J5. H. Tabkhi and G. Schirner, “A Joint SW/HW Approach for Reducing Register File Vulnerability“, ACM Transactions on Architecture and Code Optimization (ACM TACO), vol.12, no.2, pp.1-28, May. 2015.

J4. H. Tabkhi, M. Sabbagh and G. Schirner, “A Power-Efficient Real-Time Solution for Adaptive Vision Algorithms”, IET Computers & Digital Techniques, vol.9, no.1, pp.16-26, Jan. 2015.

J3. H. Tabkhi, R. Bushey and G. Schirner, “Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs”, IEEE Embedded Systems Letters, vol.6, no.4, pp.65-68, Dec. 2014.

J2. H. Tabkhi and G. Schirner, “Application-Guided Power Gating Reducing Register File Static Power”, IEEE Transactions on Very Large Scale Integration (TVLSI), vol.22, no.12, pp.2513-2526, Dec. 2014.

J1. A. PatooghyG. S Miremadi and H. Tabkhi, “A Reliable and Power Efficient Flow-Control Method to Eliminate Crosstalk Faults in Network-on-Chips“, Microprocessors and Microsystems – Embedded Hardware Design, vol 35, no. 8, pp. 766-778, Nov. 2011.


Peer-Reviewed Conference Papers

C20. A. MomeniH. TabkhiG. Schirner and D. Kaeli, ” Hardware thread reordering to boost OpenCL throughput on FPGAs”, International Conference on Computer Design (ICCD), Phoenix (AZ), Oct. 2016.

C19. A. MomeniH. TabkhiG. Schirner and D. Kaeli, “OpenCL-based Optimizations for Acceleration of Object Tracking on FPGAs and GPUs”, International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), in Conjunction with CGO’16, Barcelona, Spain, Mar. 2016.

C18. H. Tabkhi, M. Sabbagh and G. Schirner, “Guiding Power/Quality Exploration for Communication-Intense Stream Processing” Great Lakes Symposium on VLSI (GLS-VLSI), Boston (MA), USA, May 2016.

C17. N. Teimouri, H. Tabkhi and G. Schirner, “Improving Scalability of CMPs with Dense ACCs Coverage”, IEEE Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 2016.

C16. M. SabbaghH. Tabkhi and G. Schirner, “Taming the Memory Demand Complexity of Adaptive Vision Algorithms“, IFIP International Embedded Systems Symposium (IESS), Foz do Iguacu, Brazil, Nov. 2015.

C15. H. TabkhiM. Sabbagh and G. Schirner, “An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction“, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Toronto, Canada, Jul. 2015.

C14. A. MomeniH. TabkhiY. UkidaveG. Schirner and D. Kaeli, “Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA“, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Boston (MA), USA, Jun. 2015.

C13. N. Teimouri, H. Tabkhi and G. Schirner, “Revisiting Accelerator-Rich CMPs: Challenges and Solutions”, ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco (CA), USA, Jun. 2015.

C12. Ch. Zhang, H. Tabkhi and G. Schirner, “A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction”, International Conference on Parallel Processing (ICPP), Minneapolis (MN), USA, Sep. 2014.

C11. H. Tabkhi, R. Bushey and G. Schirner, “Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs”, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, Jun. 2014 (best paper runner-up).

C10. H. Tabkhi, R. Bushey and G. Schirner, “Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision”, IEEE Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), Monterey (CA), USA, Nov. 2013.

C9. R. Bushey, H. Tabkhi and G. Schirner, “Flexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision Processor”, IEEE Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), Monterey (CA), USA, Nov. 2013 (invited).

C8. R. Bushey, H. Tabkhi and G. Schirner, “A Novel Quantitative ESL Based SOC Architecture Exploration Methodology”, Analog Devices General Technical Conference (ADI GTC), Apr. 2013 (industry conference).

C7. H. Tabkhi and G. Schirner, “AFReP: Application-guided Function-level Registerfile Power-gating for Embedded Processors”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose (CA), USA, Nov. 2012.

C6. H. Tabkhi and G. Schirner, “ARRA: Application-guided Reliability-enhanced Registerfile Architecture for Embedded Processors”, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz (CA), USA, Oct. 2012.

C5. H. Tabkhi and G. Schirner, “Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability”, IEEE Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 2012.

C4. A. PatooghyH. Tabkhi and G. S Miremadi, “An Efficient Method to Reliable Data Transmission in Network-on-Chips“, Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Lille, France, Sep. 2010.

C3. A. PatooghyH. Tabkhi and G. S Miremadi, “RMAP: A Reliability-Aware Application Mapping for Network-on-Chips“, International Conference on Dependability (DEPEND), Venice/Mestre, Italy, Jul. 2010.

C2. H. Ghasemzadeh-MohammadiH. TabkhiG. S Miremadi and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic“, IEEE International Conference on Microelectronics (ICM), Sharjah, United Arab Emirates, Dec. 2008.

C1. H. TabkhiG. S Miremadi and A. Ejlali, “An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors“, IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT), Cambridge (MA), USA, Oct. 2008.


Poster Abstracts

WP2. A. Momeni*, H. Tabkhi, G. Schirner and D. R. Kaeli, “Bridging Architecture and Programming for Throughput-Oriented Vision Processing”, International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey (CA), USA, Feb. 2015.

WP1. H. Tabkhi, M. Sabbagh* and G. Schirner, “A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution”, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston (MA), May 2014.