ECGR 4433/5133 VLSI System Design

VLSI System Design

ECGR 4433/5133

Spring 2011

   

Lecture

Timings

 
         5 pm – 7:30 pm Monday      

Room
                              Woodward 140

Office Hours
                  
Monday     3:30 pm – 5 pm @ Woodward 235B

 
Instructor
Dr. Arindam Mukherjee
Course Description
       This course is designed for students with a preliminary background in logic system design. The course introduces the techniques used in the synthesis, physical design and fabrication of  VLSI chips, specifically targeting Embedded Chip MultiProcessors (CMPs). The course begins with the fundamental elements of transistor based switching, different logic families, and gradually builds up processor components and cores, ultimately leading up the design of an Embedded CMP. Fundamental processor architectural concepts are introduced, with focus on Embedded low-power real-time constrained CMPs. In addition, students will be introduced to leading Industrial CAD tools used today for VLSI and ULSI chip design.
 
Course Objectives
    The primary goal of this course is to introduce students to VLSI System-on-a-Chip Design, and to give the participants the concepts and techniques necessary to design and verfiy a low-power real-time constrained Embedded Chip MultiProcessor in ultra-Deep-Sub-Micron technology. This is a very practical, results-oriented course that will provide knowledge and skills that can be applied immediately.

 
Prerequisites
Logic System Design II (ECGR 3181)

Textbook     
Modern VLSI Design: IP-Based Design (4th Edition) by Wayne Wolf (Hardcover – Dec 31, 2008)
Grading
Midterm – 30%, Final – 30%, Project ? 40%
Lecture Notes
Set1   
Set2   
Set3   
Set4   
Set5   
Set6   
Set7   
Set8   
Set9   
Set10   
Set11   
Set13   
Set14
Resources
Spice Links,
Cadence Spice Manual
Spice Examples Example: FPU of SUN UltraSPARC T1:
FPU.vhd 
full adder
Synopsys Design Vision Simplified Manual
Design Vision More Detailed Manual
Design Vision – Timing Analysis
Final Design Vision Manual
Design Vision Database in 45nm Technology [ .db attachment]
Cadence Encounter Simplified Manual
Final Encounter Manual
Needed files for Encounter
RC Output File Formats
Example RC Files                                 
Class Demos                             
                                                        
inverter.doc
                                Course Project                               
                                                                                                                
Location of SPICE netlists                                                        
Contents of your final report                                                                           
Design Rules